1. Field of the Invention
This invention relates to a digital/analog conversion circuit, and more particularly to a cyclic digital/analog conversion circuit.
2. Description of the Related Art
A digital/analog converter (hereinafter referred to simply as DAC) is a circuit for converting a digital signal which has been subject to various digital processes into an analog signal so as to be outputted as a real signal, and is one of basic components of electric apparatus. The DAC is used widely in television receivers, audio apparatus, communication apparatus and so forth. In the apparatus mentioned, the DAC is used as a circuit for converting a digital signal which has been subject, for example, to an image process or a sound process into an analog signal to be outputted to a display unit or a speaker. Further, the DAC is used as a circuit for converting a digital signal which has been subject to various coding and/or decoding processes into an analog signal to be signaled to a communication line.
Various performances which may be required for the DAC differ depending upon the application, and small area occupation and low current consumption are representative ones of the performances. For example, in a driver application for a liquid crystal display (LCD) unit, a number of DACs equal to the number of columns of the LCD unit may be required. Where the number is great, it reaches approximately 1,000, and therefore, small area occupation and low power consumption of the individual DACs provide significant merits.
As one of DACs which satisfy small area occupation and low power consumption, a cyclic DAC is known since the olden times of the 1970's.
FIG. 13 shows an example of a configuration of a general cyclic DAC. Referring to FIG. 13, the cyclic DAC shown is basically composed of two capacitors (C21 and C22) having an equal electrostatic capacitance and switches (SW31, SW32, SW33 and SW34), and digital/analog converts a serial bit string.
Action of the cyclic DAC is described briefly with reference to FIG. 13.
The switch SW31 selects and outputs a voltage corresponding to an input bit to the switch SW32. For example, the switch SW31 selects a reference voltage (Vref) when the value of the input bit is “1”, but selects the ground (GND) when the value of the input bit is “0”.
The switch SW32 plays a role of sampling. When the switch SW32 is on, a voltage corresponding to the input bit value is applied to the capacitor C21 through the switches SW31 and SW32. At this time, the switch SW33 is in an off state, and a previous voltage is held in the capacitor C22.
The switch SW33 plays a role of charge-sharing. If the switch SW33 is switched on, then the capacitors C21 and C22 are connected in parallel, and charge accumulated in the two capacitors C21 and C22 is shared equally. This implements an arithmetic operation of ½ multiplication which is most significant in digital/analog conversion.
The switch SW34 implements resetting of the charge of the capacitor C22.
FIG. 14 illustrates sampling and charge sharing action of the cyclic DAC shown in FIG. 13.
Referring to FIG. 14, in order to sample charge in accordance with an input bit value into the capacitor C21, the switch SW32 is switched on and the switch SW33 is switched off while the switch SW31 selects a voltage corresponding to the input bit value. For example, when the input bit value is “1” as seen in FIG. 14, the switch SW31 selects the reference voltage Vref, and the capacitor C22 receives the reference voltage Vref as an input thereto through the switch SW32. At this time, the switch SW33 is in an off state, and consequently, the capacitor C22 holds a previous voltage Vx.
After the sampling is completed, the switch SW32 is switched off and the switch SW33 is switched on so that the capacitors C21 and C22 are connected in parallel. Since the capacitors C21 and C22 have an equal electrostatic capacitance, one half of the entire charge is shared out to each of the capacitors C21 and C22, and the voltage of each of the capacitors C21 and C22 is substantially equal to (Vref+Vx)/2. When a next sampling is performed by the capacitor C21, a result of the preceding charge sharing is retained in the capacitor C22.
As described hereinabove, the cyclic DAC shown in FIG. 13 successively samples charge in accordance with the input bit value into the capacitor C21 and successively charges, in parallel to the sampling action, one half of the sum of the charge retained already in the capacitor C22 and the charge sampled newly into the capacitor C21 into the capacitor C22.
This action of the cyclic DAC can be represented by such a feedback system as seen in FIG. 15.
In the feedback system shown in FIG. 15, a multiplication section 102 multiplies an addition result outputted from an addition section 101 by ½. A delay section 103 retains a result of the multiplication of the multiplication section 102 and outputs the retained multiplication result to the addition section 101 when an arithmetic operation is to be performed by the addition section 101. The addition section 101 arithmetically operates the sum of a signal successively inputted for each bit and the output signal of the delay section 103.
Where the bits of the input bit string (L bits) are individually represented by D1, D2, D3, . . . , DL in order from the LSB side, the output voltage Vout of the cyclic DAC shown in FIG. 13 is represented ideally by the following expression (1):
                                                                        V                out                            =                                                (                                                                                    (                                                                                                            (                                                                                                                                    ⋯                                    ⁡                                                                          (                                                                                                                                                                    (                                                                                                                                                                                            D                                                  1                                                                                                ·                                                                                                  1                                                  2                                                                                                                                            +                                                                                              D                                                2                                                                                                                                      )                                                                                    ·                                                                                      1                                            2                                                                                                                          +                                                                                  D                                          3                                                                                                                    )                                                                                                        ·                                                                      1                                    2                                                                                                  +                                ⋯                                +                                                                  D                                                                      L                                    -                                    2                                                                                                                              )                                                        ·                                                          1                              2                                                                                +                                                      D                                                          L                              -                              1                                                                                                      )                                            ·                                              1                        2                                                              +                                          D                      L                                                        )                                ·                                  1                  2                                ·                                  V                  ref                                                                                                        =                                                (                                                                                    1                        2                                            ⁢                                              D                        L                                                              +                                                                  1                                                  2                          2                                                                    ⁢                                              D                                                  L                          -                          1                                                                                      +                                                                  1                                                  2                          3                                                                    ⁢                                              D                                                  L                          -                          2                                                                                      +                    ⋯                    +                                                                  1                                                  2                                                      L                            -                            1                                                                                              ⁢                                              D                        2                                                              +                                                                  1                                                  2                          L                                                                    ⁢                                              D                        1                                                                              )                                ·                                  V                  ref                                                                                                        =                                                V                  ref                                ·                                                      ∑                                          k                      =                      1                                        L                                    ⁢                                                            D                      k                                                              2                                              L                        -                        k                        -                        1                                                                                                                                                    (        1        )            
From the expression (1), it can be recognized that digital/analog conversion can be implemented certainly by the cyclic DAC having the configuration described hereinabove with reference to FIG. 13.
Incidentally, the maximum effective bit number (effective number of bits: ENOB) of the cyclic DAC normally depends upon a mismatch in electrostatic capacitance of two capacitors (C21 and C22). In particular, the electrostatic capacitances of the two capacitors do not fully coincide with each other, and this makes a factor of restricting the ENOB. Where the capacitance values of the capacitors C21 and C22 are represented by “A” and “B”, the output voltage Vout of the cyclic DAC represented by the expression (1) can be represented as given by the following expression (2):
                              V          out                =                              V            ref                    ·                                    ∑                              k                =                1                            L                        ⁢                                                            AB                                      L                    -                    k                                                                                        (                                          A                      +                      B                                        )                                                        L                    -                    k                    +                    1                                                              ⁢                              D                k                                                                        (        2        )            
Here, if the electrostatic capacitance B is represented by “B=A×(1+x)” and the mismatch of the electrostatic capacitances A and B is represented by a variable x, then the output voltage Vout of the cyclic DAC represented by the expression (2) can be represented by the following expression (3):
                              V          out                =                              V            ref                    ·                                    ∑                              k                =                1                            L                        ⁢                                                                                (                                          1                      +                      x                                        )                                                        L                    -                    k                                                                                        (                                          2                      +                      x                                        )                                                        L                    -                    k                    +                    1                                                              ⁢                              D                k                                                                        (        3        )            
From the difference between the expressions (3) and (1), the error amount ΔVout of the output voltage Vout by the mismatch between the electrostatic capacitances A and B can be represented as given by the following expression (4):
                              Δ          ⁢                                          ⁢                      V            out                          =                              V            ref                    ·                                    ∑                              k                =                1                            L                        ⁢                                          {                                                                                                    (                                                  1                          +                          x                                                )                                                                    L                        -                        k                                                                                                            (                                                  2                          +                          x                                                )                                                                    L                        -                        k                        +                        1                                                                              -                                      1                                          2                                              L                        -                        k                        +                        1                                                                                            }                            ·                              D                k                                                                        (        4        )            
FIG. 16 illustrates a relationship between the error amount ΔVout and input data where the bit length L is L=11 and the mismatch x is x=0.002 (0.2%). The axis of abscissa indicates the value of the input data expressed in the decimal notation, and the axis of ordinate indicates the error amount ΔVout normalized with the voltage value (Vref/2L) of 1 LSB.
As can be seen from the result illustrated in FIG. 16, the error amount ΔVout with regard to the input data of a particular value is greater than 1 LSB. Accordingly, where the mismatch x in electrostatic capacitance is 0.2%, the ENOB exhibits a limit at approximately nine bits.
In recent years, together with reduction in the area and increase of the operating speed of digital circuits, signals of a progressively high resolution, that is, of an increasing number of bits, are handled. This inevitably may require a higher ENOB for DACs. Further, since to provide a sufficient ENOB performance to DACs provides enhancement in withstanding property against a production dispersion of circuit characteristics, this contributes also to enhancement of the yield of circuits. Accordingly, also for cyclic DACs, it is demanded to implement a higher ENOB which exceeds a limit to the ENOB provided by a mismatch in electrostatic capacitance.
Various DACs directed to increase of the ENOB are known and disclosed, for example, in “Reduction Methods of Capacitor Mismatch Errors In Switched-Capacitor A/D, D/A converters”, ISCAS'88, United States, June 1888, Vol. 3, p. 2813 to 2816 (hereinafter referred to as Non-Patent Document 1). Another DAC is disclosed in “Two-capacitor DAC with compensative switching”, Electronics Letter, United States, 1995, Vol. 31, p. 1435 to 1437 (hereinafter referred to as Non-Patent Document 2).
In particular, Non-Patent Document 1 proposes a cyclic DAC which additionally includes a sequence for detecting and correcting a mismatch in electrostatic capacitance.
FIG. 17 illustrates the correction sequence.
Referring to FIG. 17, a capacitance mismatch between two capacitors C21 and C22 is detected, and if the capacitance mismatch is higher than a fixed value, then a very small capacitor is added to that one of the capacitors C21 and C22 which has a lower capacitance value (in the example of FIG. 17, the capacitor C21). Then, a capacitance mismatch between the two capacitors is detected, and if the mismatch is still higher than the fixed value, then another very small capacitor is added. Such a sequence as just described is repeated until the mismatch becomes lower than the fixed value. Thereafter, digital/analog conversion action is performed.
On the other hand, Non-Patent Document 2 proposes a technique which does not involve correction of a capacitance mismatch itself but adopts a compensative switching method which performs switching so as to cancel an effect of a mismatch.
FIG. 18 shows an example of a configuration of a cyclic DAC which performs digital/analog conversion using the compensative switching method. Referring to FIG. 18, the cyclic DAC shown includes capacitors C21 and C22, switches SW35 and SW36 for applying a reference voltage Vref to the capacitors C21 and C22, respectively, switches SW37 and SW38 for resetting charge of the capacitors C21 and C22, respectively, and a switch SW39 for connecting the capacitors C21 and C22 in parallel. In the cyclic DAC shown in FIG. 18, since sampling switches are provided individually for the two capacitors C21 and C22, any of the capacitors C21 and C22 can be used for sampling.
According to the compensative switching method, an error caused by a mismatch in electrostatic capacitance is compensated for by performing sampling, which is usually performed by one of two capacitors (in the cyclic DAC shown in FIG. 13, the capacitor C21), using both capacitors. In particular, for each bit of an input bit string, a cumulative error by mismatches at the inputting timing is calculated, and a capacitor of an object of sampling is selected so that the error produced by the sampling of the bit may cancel the cumulative error until then.